During the 23rd Synopsys EDA Interoperability Forum an update was given on the status of the IPLnow efforts (http://www.iplnow.com). The majority of the new work in iPDK has to do with Analog Constraints. Here are some of my thoughts concerning analog constraints:
Constraints are a type of meta data that describe behavior expected in a circuit. For our purposes constraints imply some particular attribute of a chip layout. Examples of a constraints include things like the width of a line, the orientation of a number of transistors, and the size of devices. Line width affects capacitance and resistance, too much or too little of each can impact a circuit in a negative manner. For circuit matching purposes devices need to be oriented in the same direction. Any matched devices need to share this same orientation, thus constraints regarding orientation are defined. Devices often need to be similar in size to match properly, thus placing size constraints is important; for example having two resistors, one 1 um by 1um versus 20um by 20um; the 20 um device will show less variation and thus much better matching characteristics.
Any system using constraints must support the following features:
You must be able to visually confirm any defined constraint.
There must be a mechanism to allow automated verification of the defined constraints similar to a DRC check, and this check must be able to be run at tape-out.
Constraints must work cell to cell, not only within a given cell.
An automated mechanism needs to exist to override electrical constraints that impair a circuits performance.
Most of these features are self evident, number 4 is not. For example, if early in a design I specify a line width of 2 um based on the current density requirements, and later the specification (and design) changes and requires 4um width, I have specified an incorrect constraint. Ideally I would like these constraints defined from some electrical parameter such as current which as the design is changed is tracked through layout. Unfortunately I suspect constraints will not be quite so flexible for a while, and we are stuck with line width. We do not want to have constraints defined that cause a circuit not to work. coming up with a solution to this will not be easy.